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The essential signal
- Five partners — LSTC, Hokkaido University, Fujifilm, GE HealthCare Japan and Belgium's imec — announced on 20 October 2026 that they will jointly develop real-time medical image-processing systems built on inference-specialised 2nm-generation AI chips, with backing from NEDO's Post-5G R&D programme.
- The stated R&D targets: medical image processing at least 5x faster and at least 10x more energy efficient than today's GPUs. These are targets, not measured results — no project chip has been fabricated yet.
- Three clinical systems are in scope: real-time CT diagnostic support (reconstruction from photon-counting CT data plus automatic organ identification), real-time ultrasound support (live overlay of prior CT/MRI images), and real-time surgical-video analysis — with demonstration trials planned at Hokkaido University Hospital and a demonstration goal of 2031.
Why would a hospital need a 2-nanometre chip?
Start with the obvious question: what business does a cutting-edge logic chip have inside a hospital? The answer begins with the sheer weight of medical data. A modern CT scanner captures anatomy in remarkable detail, but turning raw detector readings into images a clinician can actually read is a heavy computational lift — and the newest detector technology multiplies that load several times over. Today's workaround is the graphics processor, which handles the maths well but was never designed to live inside a compact medical device.[1]
The mismatch is practical as well as physical. Sending scans to the cloud for processing runs into patient-data restrictions, bandwidth limits and the latency requirements that clinical work will not tolerate [1]. And the clinical workload is overwhelmingly inference — running finished models on new scans — rather than the training work GPUs were built to dominate [1]. The Japanese consortium's bet is straightforward: a chip specialised for inference, at a leading-edge process node, should beat a general-purpose GPU at exactly this job [1].[1]
The 20 October announcement: five partners, one plan
On 20 October 2026, five organisations announced they would jointly develop real-time medical image-processing systems built around inference-specialised, 2nm-generation AI chips: Japan's Leading-edge Semiconductor Technology Center (LSTC), Hokkaido University, Fujifilm, GE HealthCare Japan, and Belgium's imec [1][2][3]. The announcement, made at a Tokyo press conference, frames the effort as a genuine joint development rather than a procurement deal — device makers, a university research base, and semiconductor specialists building the system together.[1][2][3]
The project was selected for NEDO's "Post-5G Information and Communication Systems Infrastructure Enhancement R&D Project / Development of Advanced Semiconductor Manufacturing Technologies (Commissioned)" [1][2]. LSTC leads the consortium, and Professor Kohsuke Kudo of Hokkaido University serves as deputy R&D director [1][2]. NEDO selection matters: it is Japan's national industrial-technology agency, and a commissioned project carries government funding and a formal development framework rather than a loose memorandum of understanding [1].[1][2][3]
The data avalanche from photon-counting CT
To understand why the consortium reaches for a new chip at all, look at what photon-counting CT does to the data budget. Unlike conventional CT, which integrates X-ray energy over a time window, photon-counting detectors register individual X-ray photons — and that brings roughly four times the resolution along with three to five times more data per scan [1]. Every gain in diagnostic detail lands directly on the image-processing pipeline.[1]
Making that reconstruction happen in real time is the challenge. Desktop-class GPUs draw on the order of 300 to 700 watts, which is awkward to cool, power and physically embed inside clinical equipment [1]. When the data volume grows three- to five-fold, that inefficiency stops being a mere inconvenience — it becomes the bottleneck standing between a better detector and a better diagnosis [1].[1]
NEDO's Post-5G programme backs the plan
The project sits inside one of Japan's large public R&D bets. Selection for NEDO's "Post-5G Information and Communication Systems Infrastructure Enhancement R&D Project / Development of Advanced Semiconductor Manufacturing Technologies (Commissioned)" means the work is being carried out under a public mandate, with the state expecting results that feed back into Japan's industrial base [1][2].[1][2][3][6]
The public money around this ecosystem has grown sharply. Japan's government approved an additional ¥631.5 billion (about $4 billion) in Rapidus subsidies in October 2026, bringing total state support for the chipmaker to roughly ¥2.6 trillion (about $16.3 billion) by the end of fiscal 2027 [3][6]. That scale of support is the backdrop to the whole announcement: the medical imaging systems and the chips that would power them are being developed as strands of the same national programme [1][2][3].[1][2][3][6]
The headline targets: five times faster, ten times more efficient
The headline figures are the ones every report leads with: image processing at least five times faster, and at least ten times more energy efficient, than today's GPUs [1][2][3]. On paper, that would transform real-time medical imaging — CT reconstructions that wait on no one, ultrasound overlays that track live anatomy, surgical video analysed as it streams.[1][2][3]
One caveat matters more than the numbers themselves: these are stated research-and-development targets, not measured results [1][2][3]. No chip has been fabricated for this project yet, and the targets describe where the consortium aims to land, not where it is. That distinction is load-bearing — because the gap between a target and a result is exactly where technology coverage most often goes quietly wrong.[1][2][3]
Who does what: the division of labour
The division of labour mirrors each partner's home turf. Fujifilm develops the AI for imaging tests and ultrasound: high-speed CT reconstruction AI and organ segmentation AI [1][2]. Hokkaido University takes AI design and evaluation — building the models and proving they work against clinical data [1][2].[1][2]
The silicon itself is LSTC's job, and LSTC includes Rapidus — the company Japan is standing up to manufacture 2nm-class logic [1][2]. In other words, the models and the hardware they run on are being co-designed inside one consortium, which is exactly how you avoid the mismatch that plagues general-purpose GPUs running specialist workloads.[1][2]
Why an inference-specialised chip beats a GPU here
Why should an inference-specialised chip beat a GPU at this job at all? Because training and inference ask very different questions of hardware. Training pushes enormous parallel arithmetic through the same operations for hours; inference takes a finished model and runs it once per scan, quickly and repeatedly, under tight power and latency budgets [1]. A chip designed around the second job can shed the generality that makes GPUs powerful — and power-hungry — for the first. (Edge-inference efficiency is a theme we have explored before in our look at [AI model quantisation for memory-constrained hardware](https://technogalaxy.tech/blogposts/ai-quantization-memory-precision-tradeoffs/).)[1]
There is also nowhere else for the compute to go. A 300-to-700-watt GPU is hard to embed in a device, and shipping raw scan data to a data centre means navigating patient-data rules, available bandwidth and the latency a live procedure demands [1]. Edge inference — the model running on the device itself — sidesteps all three, provided the chip is efficient enough to live there. That is the niche the 2nm design is aiming to fill [1].[1]
System one: real-time CT diagnostic support
The first of the three clinical systems targets CT directly: real-time diagnostic support that performs fast image reconstruction from photon-counting CT data and automatically identifies organs in the resulting images [1][2]. Reconstruction and segmentation are the two halves of one workflow — first build the image, then label what is in it — and the project treats them as a single accelerated pipeline.[1][2]
The concrete figures reported by Mynavi Tech+ put numbers on the ambition: CT reconstruction rising from about 5 slices per second on current GPUs to 25 per second, and organ segmentation across roughly 1,000 anatomical classes dropping from around 25 seconds to 5 seconds or less [1]. Those remain targets, but they show what "five times faster" looks like in practice — a radiologist's workflow compressed from tens of seconds to single ones.[1][2]
System two: real-time ultrasound support
The second system tackles ultrasound: real-time support that overlays the live ultrasound image with previously captured CT or MRI images of the same patient [1][2]. Fusing a live view with a prior scan — registration — lets the operator see structures the probe alone cannot resolve, anchored to the anatomy as it moves.[1][2]
The target here is registration at 15 frames per second [1] — fast enough that the overlay tracks the probe without perceptible lag. Ultrasound is the most operator-dependent of the major imaging modalities, so a live, correctly registered reference image is less a convenience than a second pair of eyes, arriving in exactly the moment it is needed.[1][2]
System three: surgical video analysis
The third system turns to the operating theatre: analysis of surgical-microscope video in real time, recognising instruments, anatomical structures and bleeding as the procedure unfolds [1][2]. Of the three systems, this is the least forgiving — the video never pauses, the field of view changes constantly, and the answer is only useful if it arrives while the surgeon can still act on it.[1][2]
That unforgiving timing is precisely why the workload lands on dedicated inference hardware. A cloud round-trip would blow the latency budget, and a general-purpose GPU would blow the power budget for equipment designed to sit beside a surgical microscope [1]. Whether the demonstrations planned for 2031 can hit that bar will be one of the project's truest tests.[1][2]
The road to 2031: milestones and first trials
The milestones reported by Mynavi Tech+ give the vision its shape: system power at roughly half that of current GPU-based setups, and a demonstration goal set for 2031 [1]. Between now and then lies the genuinely hard part — designing the chip, taping it out, fabricating it at 2nm, and proving the whole system in a clinical setting.[1][3]
The first clinical proving ground is named: demonstration trials are planned at Hokkaido University Hospital [1]. At the Tokyo press conference, LSTC and Rapidus chairman Tetsuro Higashi put the intent in plain terms: "We want to make use of cutting-edge semiconductors to develop technologies that are helpful at medical sites" [1][3].[1][3]
The fab it depends on: Rapidus's 2nm race
Everything in this plan passes through one fab. Rapidus is expected to manufacture the 2nm chips, and it is working under contract for IBM — building on IBM process technology, with a partnership with imec behind it [3][4][5]. The company's pilot line has been running since April 2025, and it confirmed working 2nm gate-all-around transistors in July 2025; mass production is targeted for the second half of 2027 at its Chitose, Hokkaido fab [3][4][5]. (For the wider context of how fabs like this get built, see our earlier piece on [the AI-defined fab](https://technogalaxy.tech/blogposts/admin-nvidia-s-cupotential-and-the-road-to-the-ai-defined-fab-d161f33b/).)[3][4][5][6]
The commercial reality is still forming. More than 60 companies are reportedly in talks over Rapidus's 2nm capacity, but none has signed a volume agreement — the company remains at pilot stage, with its yields still to prove [4]. Fujifilm deepened its own commitment with a ¥5 billion (about $31.6 million) investment in Rapidus in February 2026, tying its semiconductor-materials business to the same fab [6]. Targets are inspiring; fabs are where targets meet physics.[3][4][5][6]
Questions, answered.
What does "2nm" mean, and why does it matter for medical AI?
"2nm" names the generation of chip-manufacturing technology Rapidus is developing — the current frontier of logic fabrication, where transistors are packed at densities far beyond earlier nodes. The consortium's logic is that this density is what makes its targets plausible: at least 5x faster image processing and at least 10x better energy efficiency than today's GPUs [1][2][3]. Those remain R&D targets, not measured results — the chips do not exist yet, and Rapidus is targeting mass production in the second half of 2027 [3][4][5].[1][2][3][4][5]
Why can't hospitals just use GPUs for this work?
Three reasons, all reported by the consortium's coverage. First, desktop-class GPUs draw roughly 300 to 700 watts, making them hard to embed in clinical devices [1]. Second, the clinical workload is inference — running finished models on new scans — not the training work GPUs were designed around [1]. Third, sending scans to the cloud runs into patient-data restrictions, bandwidth limits and latency that live procedures will not tolerate [1]. An inference-specialised chip at the edge sidesteps all three.[1]
When will these AI medical imaging systems actually be available?
The honest answer is: not soon. The consortium's demonstration goal is 2031, with demonstration trials planned at Hokkaido University Hospital [1]. Before that, the chip itself has to be designed, fabricated at 2nm and proven — Rapidus is targeting mass production for its 2nm process in the second half of 2027 [3][4][5]. Everything on this timeline is a target, not a commitment.[1][3][4][5]
What is NEDO's Post-5G semiconductor programme?
It is the Japanese public R&D programme that selected this project: formally the "Post-5G Information and Communication Systems Infrastructure Enhancement R&D Project / Development of Advanced Semiconductor Manufacturing Technologies (Commissioned)" [1][2]. Commissioned-project status means the research is carried out under a public mandate, with results expected to feed back into Japan's industrial base — in this case, domestic advanced-semiconductor manufacturing capability [1][2].[1][2]
What is photon-counting CT, and why does it need more computing power?
Photon-counting CT is a newer detector technology that registers individual X-ray photons, rather than integrating X-ray energy over a time window the way conventional CT does. It brings roughly four times the resolution — but also three to five times more data per scan [1]. That data has to be reconstructed into images, and doing it fast enough for real-time clinical use is exactly the workload the consortium's 2nm inference chips are meant to take on [1][2].[1][2]
Read the sources.
- Japan Consortium Wins NEDO Funding for 2nm Medical Imaging AILet's Data Science · Accessed 2026-10-29
- LSTC Bets on 2nm Chips for Medical AI, Targeting 5x Speed and 10x EfficiencyTai Semicon (Medium) · Accessed 2026-10-29
- Rapidus Advanced Chips to Power Medical AI; LSTC, Hokkaido University and Fujifilm Team UpAlo Japan · Accessed 2026-10-29
- As AI inflates gadget prices, Japan's Rapidus races to add advanced chip supplyJStories · Accessed 2026-10-29
- NEDO Approves Rapidus' FY2026 Plan and Budget for 2nm Semiconductor ProjectsRapidus Corporation · Accessed 2026-10-29
- Why Fujifilm Is Investing US$18m in Arizona Chip ProductionManufacturing Digital · Accessed 2026-10-29
Contributor articles and source links do not guarantee error-free reporting. See our editorial policy.
